Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a small device volume and at a low cost. Another requirement for wireless communication device design is to have low power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems may comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering logic, etc, as well as baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation functions, processing logic, etc. and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are defined for communicating between the respective sub-systems.
In the field of mobile communication devices, a standardisation body, the MIPI (Mobile Industry Processor Interface) Alliance, consisting primarily of semiconductor and mobile phone manufacturers has been formed to define various sub-system interfaces. Standardisation efforts within the MIPI Alliance include the DigRF working group, which is focused on developing specifications for interfaces between wireless mobile RFICs (Radio Frequency Integrated Circuits) and BBICs (BaseBand Integrated Circuits), and the Physical Layer (PHY) working group, which is charted with specifying high-speed physical layer designs to support multiple application requirements, such as the M-PHY layer, a high speed, embedded clock design.
DigRF utilises the M-PHY physical layer to transport air interface sample information between Integrated Circuits (ICs). The MIPI DigRF and M-PHY standards ensure that compliant RF and baseband ICs can communicate directly with each other. This removes the need for an intermediate mixed signal device. The standard places few constraints on the internal architectures of the ICs, to maximise scope for suppliers to differentiate through innovation and design. Likewise the MIPI Unified Protocol (Unipro) standard can utilise the MIPI M-PHY standard to communicate information between such devices as an applications processor and an imaging or camera sub-system.
Within the MIPI DigRF parlance, the transmit data is referred to as ‘TxData’ in a direction from the BBIC to the RFIC and the receive data is referred to as ‘RxData’ routed in a direction from the RFIC to the BBIC.
Data transmission between a baseband (BB) line drive and RF line receiver is asynchronous in nature. Consequently, the uplink controller does not have any knowledge about the correct clock phase to be used for extracting the data. Thus, a synchronization pattern is transmitted close to the start of a frame to facilitate synchronization.
Either a phase picking or CDR (clock data recovery) system is required to sample the data correctly. In a CDR system the embedded clock is derived from the data stream and used to sample the incoming stream. As a result, CDR mechanisms are a key functional element of the interface mechanism.
The receiving end of the interface is required to provide a means of adjusting the phase sample of the selected clock speed (which may, for example, be running at 1248 MHz or 2496 MHz for high speed), so as to centre the data sampling point in the centre of the data bit period, as understood by those skilled in the art, and hence ensure reliable communication.
One option available is to make use of an embedded clock signal in the data stream. The embedded clock can be used for alignment of the sample clock on the receive side of the interface. Clock Data Recovery (CDR) techniques can be employed to extract the transmit clock from the received data stream. CDR techniques are exploited extensively in modern serial communication links to minimise errors on the links. The primary purpose of the CDR is to recover the clock signal, or the phase of the clock signal, in order to optimally sample the incoming data stream, and thereby ensure a low BER (Bit Error Rate). The CDR is responsible for tracking incoming data over a range of bit-rates.